by bitwiseblog.com | Apr 18, 2026 | Blog, Systemverilog, UVM
Stop Memorizing Syntax. Start Modeling Intent. When it comes to understanding SystemVerilog functions vs tasks, most engineers start with a quick checklist: functions return a value, tasks can consume time. That description is accurate, but it stops right where things...
by Anup Reddy | Feb 15, 2026 | Blog, UVM
What You Actually Use Every Day If you read most explanations of the UVM factory, they begin with APIs. They explain set_type_override_by_type(), show a minimal example, and stop there. What’s missing is the architectural context: Why experienced verification...
by Anup Reddy | Nov 29, 2025 | Blog, UVM
Introduction As UVM testbenches evolve from simple setups to complex, multi-layered environments, configuration management becomes one of the most critical and confusing aspects of maintaining control and flexibility. Every testbench you build, regardless of its...
by Anup Reddy | Mar 2, 2024 | Systemverilog, UVM
Introduction In ASIC verification, we all use a method known as Metric Driven Verification but we don’t use that term much. Instead we always refer to it as Coverage Driven Verification. Although, both the terms means the same thing to some extent. There are...
