Basic SystemVerilog Course

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About Course

A free beginner-friendly SystemVerilog course covering types, vectors, operators, simulation processes, arrays, functions, tasks, modules, interfaces, classes, assertions, constrained random verification, and coverage.

Course Content

Module 1 — How SystemVerilog Thinks About Types
Learn the two axes of SystemVerilog typing: value states and assignment kind. This module builds the mental model behind logic, bit, nets, variables, X/Z, and typedefs.

Data Types and Kinds in SystemVerilog
Integer Types in SystemVerilog
`typedef` in SystemVerilog

Module 2 — Vectors, Packed Types, and Structs
Move from single-bit signals to packed vectors, enums, structs, and strings so you can represent realistic hardware data cleanly.

Module 3 — Operators
Understand the operators that matter in RTL and verification, including equality variants, reductions, concatenation, replication, and inside.

Module 4 — Processes and Simulation Time
Build a working model of concurrent simulation, procedural blocks, assignment scheduling, control flow, and timing controls.

Module 5 — Arrays
Use the right array form for memories, payloads, queues, scoreboards, and sparse data structures.

Module 6 — Functions and Tasks
Create reusable procedural code and know when zero-time functions differ from time-consuming tasks.

Module 7 — Modules, Ports, and Hierarchy
Declare, parameterize, instantiate, connect, and debug module hierarchies using modern SystemVerilog style.

Module 8 — Interfaces and Modports
Bundle related signals with interfaces, enforce views with modports, and pass interfaces into class-based testbenches.

Module 9 — Parallel Execution: `fork…join`
Launch and synchronize concurrent testbench activities safely using fork/join variants and process-control patterns.

Module 10 — Introduction to Classes
Begin SystemVerilog OOP with classes, handles, constructors, inheritance, and transaction-style modeling.

Module 11 — Immediate Assertions
Replace manual checks with immediate assertions and learn the entry point into assertion-based verification.

Module 12 — Introduction to Constrained Random Verification
Use random variables, constraints, and randomize hooks to generate legal stimulus at scale.

Module 13 — Introduction to Functional Coverage
Measure what your random tests actually exercised using covergroups, coverpoints, and bins.

A course by

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Requirements

N Digital Design
N Basic knowledge of verilog
N Any programming language

Audience

N Graduates students
N Post graduate students
N Working professionals in DV

Basic SystemVerilog Course

About Course

What Will You Learn?

Course Content

Module 1 — How SystemVerilog Thinks About Types Learn the two axes of SystemVerilog typing: value states and assignment kind. This module builds the mental model behind logic, bit, nets, variables, X/Z, and typedefs.

Data Types and Kinds in SystemVerilog

Integer Types in SystemVerilog

`typedef` in SystemVerilog

Module 2 — Vectors, Packed Types, and Structs Move from single-bit signals to packed vectors, enums, structs, and strings so you can represent realistic hardware data cleanly.

Scalars, Vectors, and Aggregates in SystemVerilog

Enums in SystemVerilog

Structures in SystemVerilog

Strings in SystemVerilog

Module 3 — Operators Understand the operators that matter in RTL and verification, including equality variants, reductions, concatenation, replication, and inside.

Operators in SystemVerilog

Module 4 — Processes and Simulation Time Build a working model of concurrent simulation, procedural blocks, assignment scheduling, control flow, and timing controls.

Processes in SystemVerilog

Procedural Statements in SystemVerilog

Module 5 — Arrays Use the right array form for memories, payloads, queues, scoreboards, and sparse data structures.

Arrays in SystemVerilog — Overview

Fixed-Size Arrays in SystemVerilog

Dynamic Arrays in SystemVerilog

Queues

Associative Arrays

Array Methods

Module 6 — Functions and Tasks Create reusable procedural code and know when zero-time functions differ from time-consuming tasks.

Functions in SystemVerilog

Tasks in SystemVerilog

Module 7 — Modules, Ports, and Hierarchy Declare, parameterize, instantiate, connect, and debug module hierarchies using modern SystemVerilog style.

Modules and Hierarchy

Parameters and Overrides

Compiler Directives

Module 8 — Interfaces and Modports Bundle related signals with interfaces, enforce views with modports, and pass interfaces into class-based testbenches.

Interfaces in SystemVerilog

Modports in SystemVerilog

Virtual Interfaces in SystemVerilog

Module 9 — Parallel Execution: `fork…join` Launch and synchronize concurrent testbench activities safely using fork/join variants and process-control patterns.

Fork-Join in SystemVerilog

Module 10 — Introduction to Classes Begin SystemVerilog OOP with classes, handles, constructors, inheritance, and transaction-style modeling.

Classes and Objects in SystemVerilog

Object Handles in SystemVerilog

Constructor in SystemVerilog

Inheritance in SystemVerilog

Module 11 — Immediate Assertions Replace manual checks with immediate assertions and learn the entry point into assertion-based verification.

SVA Overview — SystemVerilog Assertions

Immediate and Deferred Assertions in SystemVerilog

Module 12 — Introduction to Constrained Random Verification Use random variables, constraints, and randomize hooks to generate legal stimulus at scale.

Constrained Random Value Generation — Overview

Constraints in SystemVerilog

Randomize Methods

Module 13 — Introduction to Functional Coverage Measure what your random tests actually exercised using covergroups, coverpoints, and bins.

Functional Coverage Overview

Covergroups

Coverpoints and Bins