About Me

Anup Reddy

With over 13 years of experience as a ASIC design verification engineer, I have developed a wealth of technical expertise and leadership skills that make me an ideal candidate for leading rigorous and effective verification.

Proficient in building constraint random test benches from scratch, creating test plans, and executing them using SystemVerilog, UVM, and C++ to ensure comprehensive verification of ASIC designs.

Experienced in implementing full functional coverage models to track verification progress and identify coverage gaps in the design. Skilled in writing complex assertions to detect design bugs early.

Possess a strong understanding of ARM-based network SOC’s and Computer Architecture, Bus Architecture, Cache/Coherency, Ethernet to enable effective testing and debug of complex designs. Proficient in protocols like AXI4, ACE