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# Learn ASIC verification | Systemverilog and UVM blog

Start learning ASIC verification by using systemverilog and UVM

## Sitemaps

- [XML Sitemap](https://bitwiseblog.com/sitemap.xml): Contains all public & indexable URLs for this website.

## Posts

- [UVM Objections - When to End?](https://bitwiseblog.com/uvm-objections-when-to-end/) - Discover what are UVM objections and how UVM objections coordinate phase activity, preventing early test endings and ensuring thorough verification.
- [SystemVerilog Functions vs Tasks](https://bitwiseblog.com/systemverilog-functions-vs-tasks/) - Understand when to use SystemVerilog functions vs tasks in verification. Learn how time, determinism, and argument semantics shape scalable UVM testbenches.
- [Practical UVM Factory](https://bitwiseblog.com/practical-uvm-factory/) - Master the UVM factory for scalable verification. Learn how type overrides and late binding prevent testbench collapse and enable seamless block-to-SoC reuse.
- [Beyond Functional Coverage: The Metric Analyzer](https://bitwiseblog.com/beyond-functional-coverage-the-metric-analyzer/) - Explore how the Metric Analyzer goes beyond functional coverage to provide insights into verification quality, effectiveness, and gap analysis in chip design.
- [UVM Analysis Communication - Behind the scenes](https://bitwiseblog.com/uvm-analysis-communication-behind-the-scenes/) - Discover how UVM analysis ports and exports enable efficient data communication and broadcasting behind the scenes in SystemVerilog testbenches.
- [Only One is Needed, No More, No Less: The Singleton](https://bitwiseblog.com/only-one-is-needed-no-more-no-less-the-singleton/) - Learn how the Singleton design pattern ensures a single instance in SV, UVM testbenches, improving control, resource sharing, and configuration consistency.
- [Natural Selection and Coverage: Can Heuristic Algorithms Improve Test Bench Coverage?](https://bitwiseblog.com/natural-selection-and-coverage-can-heuristic-algorithms-improve-test-bench-coverage/) - [et_pb_section fb_built=”1″ _builder_version=”4.23.2″ _module_preset=”default” global_colors_info=”{}”][et_pb_row _builder_version=”4.23.2″ _module_preset=”default” global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.23.2″ _module_preset=”default” global_colors_info=”{}”][et_pb_text _builder_version=”4.26.1″ _module_preset=”default” text_font=”||||||||” global_colors_info=”{}”]In the realm of verification, coverage is essential in ensuring the closure on the functionality of complex systems. However, as systems become more intricate, achieving high test coverage can be a daunting challenge. There will be several manual iterations, reviews
- [Know Your Configuration (UVM's - KYC)](https://bitwiseblog.com/know-your-configuration-uvms-kyc/) - Learn how to manage structural and functional configurations in UVM testbenches using config_db and factory overrides. Includes examples and best practices.
- [SystemVerilog Macros: Benefits, Pitfalls, and Best Practices](https://bitwiseblog.com/systemverilog-macros-explained-benefits-pitfalls-examples-and-best-practices/) - Learn how SystemVerilog macros work with examples, benefits, pitfalls, and best practices. A complete guide for verification engineers and UVM testbenches.

## Pages

- [Blog](https://bitwiseblog.com/) - Explore advanced ASIC verification using SystemVerilog and UVM — practical tutorials, best-practices and insights from an experienced verification engineer.
- [Courses](https://bitwiseblog.com/courses/) - [et_pb_section fb_built=”1″ _builder_version=”4.27.3″ background_color=”#f7f9fc” custom_padding=”56px|0px|36px|0px|false|false” global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_row _builder_version=”4.27.3″ max_width=”1120px” custom_padding=”0px||0px||false|false” global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_column type=”4_4″ _builder_version=”4.16″ global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_text _builder_version=”4.27.3″ text_text_color=”#4b5565″ text_font_size=”17px” text_line_height=”1.8em” header_font=”|700|||||||” header_text_color=”#121826″ header_font_size=”44px” header_line_height=”1.15em” max_width=”760px” module_alignment=”left” global_colors_info=”{}” theme_builder_area=”post_content”]CoursesFree, practical verification courses built from bitwiseblog notes, examples, and engineering workflows.[/et_pb_text][/et_pb_column][/et_pb_row][/et_pb_section][et_pb_section fb_built=”1″ _builder_version=”4.27.3″ background_color=”#ffffff” custom_padding=”42px|0px|64px|0px|false|false” global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_row _builder_version=”4.27.3″ max_width=”1120px” custom_padding=”0px||0px||false|false” global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_column type=”4_4″ _builder_version=”4.16″ global_colors_info=”{}” theme_builder_area=”post_content”][et_pb_text _builder_version=”4.27.3″
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- [About](https://bitwiseblog.com/about/) - [et_pb_section fb_built=”1″ _builder_version=”4.26.1″ _module_preset=”default” global_colors_info=”{}”][et_pb_row column_structure=”3_4,1_4″ _builder_version=”4.26.1″ _module_preset=”default” global_colors_info=”{}”][et_pb_column type=”3_4″ _builder_version=”4.26.1″ _module_preset=”default” global_colors_info=”{}”][et_pb_blurb title=”Empowering Verification Engineers to Build Better SoCs” use_icon=”on” font_icon=”||fa||400″ icon_color=”#E02B20″ icon_placement=”left” image_icon_width=”49px” content_max_width=”1100px” _builder_version=”4.26.1″ _module_preset=”default” header_level=”h2″ text_orientation=”justified” module_alignment=”left” custom_margin=”|||0px|false|false” custom_padding=”|||0px|false|false” global_colors_info=”{}”] Welcome to BitwiseBlog — your dedicated resource for mastering ASIC design verification through practical, high-impact insights. With 15+ years of real-world
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## Lessons

- [Why do we need to describe Hardware?](https://bitwiseblog.com/courses/systemverilog-basics/lessons/why-do-we-need-to-describe-hardware/) - [et_pb_section fb_built=”1″ admin_label=”section” _builder_version=”4.16″ global_colors_info=”{}”][et_pb_row admin_label=”row” _builder_version=”4.16″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_text _builder_version=”4.27.6″ _module_preset=”default” global_colors_info=”{}”] Why do we need to describe Hardware? In digital design, we often begin with simple techniques such as truth tables, Karnaugh maps, Boolean equations, logic gates, multiplexers, decoders, and flip-flops. These methods are very useful for
- [Data Types and Kinds in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/data-types-and-kinds-in-systemverilog/) - [et_pb_section fb_built=”1″ _builder_version=”4.27.0″ _module_preset=”default” custom_padding=”40px|0px|40px|0px|false|false” global_colors_info=”{}”][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px” global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default” global_colors_info=”{}”][et_pb_text _builder_version=”4.27.0″ _module_preset=”default” text_font_size=”16px” header_3_font=”|700|||||||” header_3_text_color=”#1a1a2e” global_colors_info=”{}”] Lesson focus: 2-state vs 4-state; nets vs variables; why logic replaced reg [/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider color=”#d0d0e0″ divider_weight=”2px” _builder_version=”4.27.0″ _module_preset=”default” custom_margin=”20px||20px||false|false” global_colors_info=”{}” column_structure=”4_4″][et_pb_column type=”4_4″ _builder_version=”4.27.6″ _module_preset=”default” global_colors_info=”{}”][/et_pb_column][/et_pb_divider][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px” global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default” global_colors_info=”{}”][et_pb_text _builder_version=”4.27.0″
- [Coverpoints and Bins](https://bitwiseblog.com/courses/systemverilog-basics/lessons/coverpoints-and-bins/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Coverpoints, automatic bins, manual named bins, ignore_bins, illegal_bins[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Coverpoints and BinsRelated: Coverage-Overview | Covergroups |
- [Covergroups](https://bitwiseblog.com/courses/systemverilog-basics/lessons/covergroups/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: covergroup, sampling triggers, sample(), iff[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]CovergroupsRelated: Coverage-Overview | Coverpoints-and-Bins | Cross-Coverage | Coverage-Options-and-Methods | Classes
- [Functional Coverage Overview](https://bitwiseblog.com/courses/systemverilog-basics/lessons/functional-coverage-overview/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Why functional coverage; CDV loop; covergroup vs code coverage vs assertions[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Functional Coverage OverviewRelated: Covergroups
- [Randomize Methods](https://bitwiseblog.com/courses/systemverilog-basics/lessons/randomize-methods/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: randomize() / randomize(null) / pre_randomize() / post_randomize()[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Randomize MethodsRelated: Randomization-Overview | Constraints | Array-Randomization |
- [Constraints in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/constraints-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: constraint blocks: relational, inside, implication ->, if-else; soft constraints[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Constraints in SystemVerilogRelated: Randomization-Overview | Randomize-Methods
- [Constrained Random Value Generation — Overview](https://bitwiseblog.com/courses/systemverilog-basics/lessons/constrained-random-value-generation-overview/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Why CRV; rand vs randc; always checking randomize() return value[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Constrained Random Value Generation —
- [Immediate and Deferred Assertions in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/immediate-and-deferred-assertions-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: assert/assume/cover; severity levels $fatal/$error/$warning/$info; deferred assertions[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Immediate and Deferred Assertions in SystemVerilogRelated: SVA-Overview | SVA-Concurrent-Assertions
- [SVA Overview — SystemVerilog Assertions](https://bitwiseblog.com/courses/systemverilog-basics/lessons/sva-overview-systemverilog-assertions/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: SVA overview: assert/assume/cover/restrict; immediate vs concurrent[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]SVA Overview — SystemVerilog AssertionsRelated: Immediate-Assertions | SVA-Boolean-Expressions |
- [Inheritance in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/inheritance-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: extends; super.new(); method overriding; what is/isn't inherited[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Inheritance in SystemVerilogRelated: Classes-and-Objects | Polymorphism | Object-Access-Privileges
- [Constructor in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/constructor-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Constructor: function new(); initializing sub-objects[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Constructor in SystemVerilogRelated: Classes-and-Objects | Constructor-Chaining | Super-and-This | Static-Properties-and-Methods
- [Object Handles in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/object-handles-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Handles as typed pointers; null; aliasing; garbage collection[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Object Handles in SystemVerilogRelated: Classes-and-Objects | Inheritance
- [Classes and Objects in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/classes-and-objects-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Class declaration; new(); properties; methods; this; value vs reference semantics[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Classes and Objects in SystemVerilogRelated:
- [Fork-Join in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/fork-join-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: fork…join / join_any / join_none; disable fork; wait fork; the loop variable capture bug[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Fork-Join
- [Virtual Interfaces in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/virtual-interfaces-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: virtual interface — how class objects reach static interfaces[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Virtual Interfaces in SystemVerilogRelated: Interfaces |
- [Modports in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/modports-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: modport for direction enforcement; master/slave/monitor views[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Modports in SystemVerilogRelated: Interfaces | Virtual-Interfaces | Processes[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0"
- [Interfaces in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/interfaces-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Interface declaration; tasks/functions inside interfaces; clocking blocks[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Interfaces in SystemVerilogRelated: Virtual-Interfaces | Modports | Processes
- [Compiler Directives](https://bitwiseblog.com/courses/systemverilog-basics/lessons/compiler-directives/) - Visual Code [et_pb_section fb_built=”1″ _builder_version=”4.27.0″ _module_preset=”default” custom_padding=”40px|0px|40px|0px|false|false”][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default”][et_pb_text _builder_version=”4.27.0″ _module_preset=”default” text_font_size=”16px” line_height=”1.8em” header_3_font=”|700|||||||” header_3_text_color=”#1a1a2e” header_3_font_size=”22px”] Lesson focus: Compiler directives: define , ifdef , timescale , default_nettype none [/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version=”4.27.0″ _module_preset=”default” color=”#d0d0e0″ divider_weight=”2px” custom_margin=”20px||20px||false|false”][/et_pb_divider][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default”][et_pb_text _builder_version=”4.27.0″ _module_preset=”default” text_font_size=”16px” line_height=”1.8em” header_3_font=”|700|||||||” header_3_text_color=”#1a1a2e” header_3_font_size=”22px”] Compiler Directives
- [Parameters and Overrides](https://bitwiseblog.com/courses/systemverilog-basics/lessons/parameters-and-overrides/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: parameter vs localparam; named overrides #(.P(val)); $clog2; elaboration-time $fatal[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Parameters and OverridesRelated: Modules-and-Hierarchy | Generate-Blocks
- [Modules and Hierarchy](https://bitwiseblog.com/courses/systemverilog-basics/lessons/modules-and-hierarchy/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Module declaration (ANSI style); port types; named connections; hierarchical names; force/release[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Modules and HierarchyRelated: Parameters-and-Overrides
- [Functions in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/functions-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Functions: return types, ref arguments, automatic, recursion; zero-time rule[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Functions in SystemVerilogRelated: Tasks | Processes
- [Associative Arrays](https://bitwiseblog.com/courses/systemverilog-basics/lessons/associative-arrays/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Associative arrays: key-value store; exists(); sparse memories[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Associative Arrays[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0"
- [Queues](https://bitwiseblog.com/courses/systemverilog-basics/lessons/queues/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Queues: push_back/pop_front; FIFO and stack patterns[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Queues[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%"
- [Dynamic Arrays in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/dynamic-arrays-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Dynamic arrays: new[], growing, delete(); payload patterns[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Dynamic Arrays in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px"
- [Fixed-Size Arrays in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/fixed-size-arrays-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Fixed-size arrays; initialization; multi-dimensional; ROM patterns[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Fixed-Size Arrays in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row
- [Arrays in SystemVerilog — Overview](https://bitwiseblog.com/courses/systemverilog-basics/lessons/arrays-in-systemverilog-overview/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Packed vs unpacked split; array type comparison[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Arrays in SystemVerilog — Overview[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0"
- [Procedural Statements in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/procedural-statements-in-systemverilog/) - Visual Code [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: if-else, unique/priority if; case/casez/casex; loops; #/@/wait timing controls[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Procedural Statements in SystemVerilogRelated: Processes | Process-Control
- [Enums in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/enums-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Named constant sets with enum; FSM state encoding; .name() method[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Enums in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px"
- [Scalars, Vectors, and Aggregates in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/scalars-vectors-and-aggregates-in-systemverilog/) - [et_pb_section fb_built=”1″ _builder_version=”4.27.0″ _module_preset=”default” custom_padding=”40px|0px|40px|0px|false|false”][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default”][et_pb_text _builder_version=”4.27.0″ _module_preset=”default” text_font_size=”16px” line_height=”1.8em” header_3_font=”|700|||||||” header_3_text_color=”#1a1a2e” header_3_font_size=”22px”] Lesson focus: Scalars, packed vectors, packed vs unpacked dimensions [/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version=”4.27.0″ _module_preset=”default” color=”#d0d0e0″ divider_weight=”2px” custom_margin=”20px||20px||false|false”][/et_pb_divider][et_pb_row _builder_version=”4.27.0″ _module_preset=”default” width=”90%” max_width=”900px”][et_pb_column type=”4_4″ _builder_version=”4.27.0″ _module_preset=”default”][et_pb_text _builder_version=”4.27.0″ _module_preset=”default” text_font_size=”16px” line_height=”1.8em” header_3_font=”|700|||||||” header_3_text_color=”#1a1a2e” header_3_font_size=”22px”] Scalars, Vectors, and Aggregates in SystemVerilog [/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider
- [`typedef` in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/typedef-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Named type aliases with typedef; why shared types live in packages[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]typedef in SystemVerilogRelated: Type-Systems | Enums
- [Integer Types in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/integer-types-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Integer types: bit, byte, int, logic, integer; signed vs unsigned; literal syntax 8'hFF[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Integer Types in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider
- [Array Methods](https://bitwiseblog.com/courses/systemverilog-basics/lessons/array-methods/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Built-in methods: sort, find, sum, unique, min, max[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Array Methods[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default"
- [Tasks in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/tasks-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Tasks: time-consuming; output/ref args; automatic for concurrent calls[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Tasks in SystemVerilogRelated: Functions | Processes | Fork-Join[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0"
- [Processes in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/processes-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: initial, always, always_ff, always_comb, always_latch; blocking = vs non-blocking
- [Operators in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/operators-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Arithmetic, relational, == vs === vs ==?; logical vs bitwise; reduction; inside; concatenation {}; replication {{}}[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Operators
- [Strings in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/strings-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: string type; $sformatf; string methods[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Strings in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column
- [Structures in SystemVerilog](https://bitwiseblog.com/courses/systemverilog-basics/lessons/structures-in-systemverilog/) - [et_pb_section fb_built="1" _builder_version="4.27.0" _module_preset="default" custom_padding="40px|0px|40px|0px|false|false"][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Lesson focus: Packed structs for register bit-fields; struct literals; copy semantics[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row _builder_version="4.27.0" _module_preset="default" width="90%" max_width="900px"][et_pb_column type="4_4" _builder_version="4.27.0" _module_preset="default"][et_pb_text _builder_version="4.27.0" _module_preset="default" text_font_size="16px" line_height="1.8em" header_3_font="|700|||||||" header_3_text_color="#1a1a2e" header_3_font_size="22px"]Structures in SystemVerilog[/et_pb_text][/et_pb_column][/et_pb_row][et_pb_divider _builder_version="4.27.0" _module_preset="default" color="#d0d0e0" divider_weight="2px" custom_margin="20px||20px||false|false"][/et_pb_divider][et_pb_row

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